1. Field of the Invention
The present invention relates to a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, to a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted/received between the timing controller and the source driver.
2. Description of the Related Art
Flat panel display devices are used in various fields because the flat panel displays are more thin and lighter than the conventional cathode ray tubes (CRTs). Specifically, display devices, such as liquid crystal displays (LCD), plasma display panels (PDP), and organic light emitting diodes (OLED), are rapidly spreading in the market while substituting for the conventional CRTs.
A flat panel display device receives a data signal from an external host system and applies the data signal to a display panel, thereby displaying an image. In this case, the flat panel display device includes a timing controller and a source driver.
That is to say, a data signal applied from an external host system is inputted to the timing controller, and the timing controller reprocesses and transmits the inputted data signal to the source driver. The source driver applies an image data voltage to the display panel using the data signal received from the timing controller.
Recently, as flat panel display devices increase in size and it is necessary to provide high quality of image, the resolution has shown a tendency to be higher. Accordingly, for data transmission between a timing controller and a source driver, a signal quality and transmission rate higher than those in the prior art is required, and a low EMI level is required for reliability of a display system.
Display devices using Reduced Swing Differential Signaling (RSDS) and mini-Low Voltage Differential Signaling (LVDS), which are conventional data transmission standards, a signal line structure in a multi-drop bus scheme is used. The RSDS scheme causes a structural impedance mismatching problem, so that signal quality decreases rapidly as a transmission rate increase, and simultaneously the EMI level becomes higher.
In order to compensate for such a problem, a Point-to-Point Differential Signaling (PPDS) technology has been proposed. The technology is to transmit a data signal through a signal line with a point-to-point structure, in which there is hardly any signal mismatching, thereby making it possible to maintain high signal quality even at a high transmission rate. However, when the number of source drivers increases, the number of data and clock signal lines increases at the same rate, thereby complicating the connections of the entire signal lines and causing the cost to increase.
FIG. 1 is a view explaining an example of a conventional protocol for data transmission between a timing controller and a source driver.
As shown in FIG. 1, a conventional protocol for data transmission between a timing controller and a source driver includes step 1 (P-I), step 2 (P-II), and step 3 (P-III) as one cycle. Step 1 corresponds to a clock training step, in which a clock signal CT for synchronizing clocks between the timing controller and the source driver is transmitted. In step 2, a control signal for the operation setup and configuration registration of the source driver is transmitted. In step 3, a data signal (RGB signal) for applying image data to a display panel is transmitted.
FIG. 2 is a view explaining a detailed transmission packet in step 2 of an example of a conventional protocol for data transmission between a timing controller and a source driver.
Referring to FIG. 2, step 2 is a step of transmitting a setup information signal of a source driver, wherein a control start packet “CTR_START packet”, control packets “CTR1 packet” and “CTR2 packet”, and a data start packet “DATA_START packet” are included. The control start packet indicates that the next packet is a control packet, the control packet carries various control signals for the configuration setup of the source driver, and the data start packet indicates that the next packet is a data packet. In step 2, a preamble packet “PREAMBLE packet” for data synchronization or the like may be included.
Tables 1 and 2 below represent the definitions of bits which are allocated to the control start packet and data start packet, respectively.
TABLE 1Bit #NameDefault0,1CKHH2-7CTR_START BITHLHLHL 8-25Dummy—26,27DMYLL
TABLE 2Bit #NameDefault0,1CKHH2-7DATA_START BITLHLHLH 8-25Dummy—26,27DMYLL
Referring to Tables 1 and 2, the control start packet includes control start bits (CTR_START; 2nd to 7th bits) for indicating that the next packet is a control packet, and reserved bits (Dummy; 8th to 25th bits); and the data start packet also includes data start bits (DATA_START; 2nd to 7th bits) for indicating that the next packet is a data packet, and reserved bits (Dummy; 8th to 25th bits). In addition, each of the control start packet and data start packet includes clock signals “CK” and “DMY” embedded with the same size as a data signal.
As described above, the conventional protocol for data transmission between a timing controller and a source driver does not include a bit error rate test (hereinafter, referred to as “BERT”) function, so that there is a difficulty in real-time sensing the bit error rate in a transmission path between the timing controller and the source driver.